Machine Learning for Electronic Design Automation

  • Date: 05/09/2017
Speaker(s):

David Z. Pan

Department of Electrical and Computer Engineering

The University of Texas at Austin, TX 78712

 

 

David Z. Pan received his PhD degree in Computer Science from UCLA in 2000. He was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. He is currently Engineering Foundation Professor at the Department of Electrical and Computer Engineering, University of Texas at Austin. He has published over 280 refereed journal/conference papers and 8 US patents, and graduated over 21 PhD students. He has served in many premier journal editorial boards and conference committees, including various leadership roles. He has received a number of awards, including the SRC Technical Excellence Award (2013), 14 Best Paper Awards, DAC Top 10 Author Award in Fifth Decade (2013), DAC Prolific Author Award (2013), ASP-DAC Frequently Cited Author Award (2015), Communications of ACM Research Highlights (2014), ACM/SIGDA Outstanding New Faculty Award (2005), NSF CAREER Award (2007), SRC Inventor Recognition Award three times, IBM Faculty Award four times, UCLA Engineering Distinguished Young Alumnus Award (2009), UT Austin RAISE Faculty Excellence Award (2014), many international CAD contest awards, among others. He is a Fellow of IEEE and SPIE.

 

 

Location: 

University of Calgary

Description: 

Machine learning is a powerful computer science technique that can derive knowledge from big data and make predictions/decisions. Since nanometer VLSI design and manufacturing have extremely high complexity and gigantic data, there is great opportunity to apply and adapt machine learning techniques in electronic design automation (EDA), e.g., VLSI physical verification such as lithography hotspot detection and VLSI physical design such as datapath-aware physical design. In this talk, I will discuss several case studies of using machine learning in various EDA applications, from lithography hotspot detection and sub-resolution assist feature (SRAF) insertion, to datapath extraction/placement and clock synthesis.

Schedule: 

Tuesday May 9th, 10:00 to 11:00 am

 

Location: ICT 424C